Regviz

Silicon Labs /EFR32FG23A010F512GM48 /SMU_S /BMPUSATD0

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as BMPUSATD0

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Silicon Labs/EFR32FG23B010F512IM40/SMU_NS/BMPUSATD0#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RADIOAES)RADIOAES 0 (RADIOSUBSYSTEM)RADIOSUBSYSTEM 0 (LDMA)LDMA 0 (RFECA0)RFECA0 0 (RFECA1)RFECA1 0 (SEEXTDMA)SEEXTDMA

Description

Set master bits to 1 to mark as a secure master

Fields

RADIOAES

RADIOAES DMA secure mode
RADIOSUBSYSTEM

RADIO subsystem masters secure mode
LDMA

MCU LDMA secure mode
RFECA0

RFECA0 secure mode
RFECA1

RFECA1 secure mode
SEEXTDMA

SEEXTDMA secure mode

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data